Methods and apparatus for implementing multi-tone receivers

ABSTRACT

Methods and apparatus for reducing phase jitter in a multi-tone, e.g., OFDM, receiver are described. A jitter compensation filter is used to process a received signal following timing recovery and/or channel compensation to reduce and/or eliminate the effect of phase jitter. Jitter compensation filter tap weights are updated after filtering the received signal based on one or more signal error measurements. The same received signal is filtered using the updated filter, and error measurements generated from the filtered signal are used to once again update the filter&#39;s tap weights. After a fixed number of filter update cycles and/or some other filter updating stop criterion being satisfied, the filter updating process is stopped and the filtered signal is used, e.g., supplied to additional receiver circuitry. The filter tap values may be reset for each block of data, with the filter update process being repeated starting from preselected initial tap weight values.

FIELD OF THE INVENTION

[0001] The present invention relates to communications systems and, moreparticular, to methods and apparatus for implementing multi-tonereceivers, e.g., orthogonal frequency division multiplexed (OFDM) signalreceivers.

BACKGROUND

[0002] As people become more mobile, the number of portable devices,e.g., notebook computers, personal data assistants, cell phones, etc.,continues to increase. The use of wireless communications techniquesenables modern portable devices to receive and transmit data fromvarious locations.

[0003] With recent advances in the Internet and other data services,users of portable devices are beginning to feel a need to receive andtransmit ever increasing amounts of data using wireless communicationstechniques.

[0004] In wireless communications a data signal, e.g., a series ofsymbols, is frequently modulated on a carrier signal, e.g., a carriertone, having a particular carrier or tone frequency. In order toincrease the amount of data that can be transmitted in a given period oftime, a plurality of different carriers may be used to transmit data,e.g., symbols, in parallel. This results in the broadcasting of what isknown as a multi-tone signal. When multi-tone signals are used, thebandwidth of the system becomes a function of the number of carriersignals in the multi-tone signal. An OFDM signal is one particular typeof multi-tone signal.

[0005] As the result of the transmission of a signal through acommunications channel and the processing of the received signal, e.g.,by a tuner and other circuitry, the transmitted signal may be distorted.For example, the communications channel may introduce amplitude and/orphase distortions. Tuners and other receiver circuitry may introducetime varying phase distortions sometimes call phase jitter. Such signaldistortions can make it difficult to recover transmitted data, e.g.,symbols, from a received signal.

[0006] Communications channel distortions are difficult to avoidparticularly in the case of over the air transmissions. Accordingly,attempts at addressing communications channel distortions have focusedprimarily on compensating for the introduced distortions at some pointin the receiver.

[0007] Phase jitter, in contrast to communications channel distortions,can be reduced or eliminated by using high quality circuits in thereceiver. Accordingly, attempts at addressing phase jitter have beenfocused on using better quality tuners and other circuits in a receiverthan those which introduce unacceptable amounts of phase jitter.

[0008] While reducing phase jitter by using high quality receivercomponents can be effective, it has the disadvantage of requiring theuse of high quality components which are usually more expensive thanlower quality components, i.e., the components which introduce morephase jitter. In consumer applications, cost is often a major concern.Accordingly, from a cost perspective, in many applications the use ofhigh quality tuners and other comparatively expensive circuitry can beundesirable.

[0009] In view of the above discussion, it should be apparent that thereis a need for methods and apparatus for increasing the amount of phasejitter which can be tolerated in a receiver, e.g., a multi-tone signalreceiver, thereby facilitating the use of relatively inexpensive tunersand/or other receiver circuitry. In addition, from a cost perspective,it is desirable that at least some methods and apparatus for enhancing areceiver's tolerance of phase jitter be relatively straight forward andinexpensive to implement.

SUMMARY OF THE INVENTION

[0010] The present invention is directed to methods and apparatus forimplementing multi-tone receiver circuitry, e.g., OFDM receivers. Inparticular, the invention is directed to reducing and/or eliminating theeffect of phase jitter in a multi-tone receiver.

[0011] In accordance with the present invention, jitter compensationfiltering is performed on a multi-tone signal, e.g., representingtransmitted symbols, to reduce and/or eliminate the effect of phasejitter on the signal. The filtering operation may be performed followingtiming recovery and/or channel compensation processing operations, e.g.,prior to demodulation.

[0012] To perform the jitter compensation filtering, a multi-tap filter,e.g., a programmable FIR filter, is used to process the received signal.The filter's tap weights are updated using at least one error estimationand/or error measurement technique. The received signal is reprocessedand the filter coefficients updated again. The filtering and filterupdating steps are performed iteratively, e.g., for a preselected numberof iterations and/or until some filter updating stop criterion aresatisfied, e.g., the filtered signal ceases to improve from the use ofthe updated filter.

[0013] In one exemplary embodiment, the jitter compensation filteroperates on a block of data. The block of data may include samplesrepresenting the symbols received on different carrier tones during thesame symbol time. After a block of data is processed by the jittercompensation filter, the filter's tap weights are reset to their initialvalues before a new block of data is processed. The resetting of thefilter tap weights reflects the fact that phase jitter may not correlatefrom block to block due to the time varying nature of the jitter.

[0014] Decision directed error measurements, pilot directed errormeasurements, and other non-decision directed error measurementtechniques, e.g., constant modulus error measurement techniques areapplied to the filtered signal to generate an error signal which can beused to update the jitter compensation filter's tap weights. Theparticular error measurement technique used at any given point of timeis selected as a function of, e.g., whether a pilot symbol is beingprocessed and/or whether a mean squared error generated from thedecision directed error estimate is below a preselected thresholdindicating that the decision directed error may be beneficial inupdating the filter tap values.

[0015] The jitter compensation techniques of the present invention allowinexpensive tuners and/or other receiver circuitry, having otherwiseexcessive phase noise, to be used in a multi-tone, e.g., OFDM, receiver.

[0016] Additional features, embodiments and benefits of the methods andapparatus of the present will be discussed below in the detaileddescription that follows.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 illustrates an OFDM receiver circuit.

[0018]FIG. 2 illustrates an ideal OFDM spectrum.

[0019]FIG. 3 is an expanded view of a portion of the ideal OFDM spectrumillustrated in FIG. 2.

[0020]FIG. 4 illustrates an idealized jitter spectrum which may beencountered when processing an OFDM signal.

[0021]FIG. 5 illustrates the effect of the jitter illustrated in FIG. 4on an OFDM spectrum such as that shown in FIG. 2.

[0022]FIG. 6 is an expanded view of a portion of the jitter affectedOFDM spectrum illustrated in FIG. 5.

[0023]FIG. 7 illustrates an OFDM receiver circuit which includes jittercompensation circuitry in accordance with the present invention.

[0024]FIG. 8 illustrates an exemplary jitter compensation filter whichcan be used in the OFDM receiver circuit shown in FIG. 7.

[0025]FIG. 9 illustrates an exemplary filter cell which may be used toimplement the jitter compensation filter of FIG. 8.

[0026]FIGS. 10 and 11 illustrate exemplary error calculation circuitsimplemented in accordance with different embodiments of the presentinvention which can be used in the jitter compensation filter of FIG. 8.

[0027]FIG. 12 shows, in the form of a graph, a set of initial jittercompensation filter tap weights used in accordance with one exemplaryembodiment of the present invention.

[0028]FIG. 13 is an exemplary OFDM output constellation beforeconvergence of the jitter compensation filter tap weights used to filterthe block of received samples representing the plotted symbols.

[0029]FIG. 14 illustrates a set of jitter compensation tap weightsresulting after six iterations of the filter refinement process of thepresent invention.

[0030]FIG. 15 illustrates an exemplary output of the jitter compensationfilter after updating the initial filter tap weights shown in FIG. 12for a sixth time.

DETAILED DESCRIPTION

[0031] The present invention relates to methods and apparatus forimplementing a multi-tone signal receiver, e.g., an OFDM signalreceiver. In accordance with various embodiments of the presentinvention, jitter compensation circuitry, e.g., a jitter compensationfilter, is included as part of the signal receiver to increase thereceiver's jitter tolerance as compared to receivers without such jittercompensation circuitry.

[0032]FIG. 1 shows a basic block diagram of an OFDM receiver circuit 100which can be used as part of an OFDM demodulator. The receiver circuit100 includes a resampling circuit 102 which may be implemented, e.g.,using an A/D converter, a fast fourier transform (FFT) circuit 104, aparallel to serial converter (P/S) 106, a channel compensation circuit108, a channel estimation circuit 110 and a timing recovery circuit 112coupled together as illustrated in FIG. 1. The various circuitsillustrated in FIG. 1 can be implemented using known techniques. Theresampling circuit 102 is responsible for sampling the received OFDMsignal and generating digital samples therefrom as a function of signaltiming information obtained from timing recovery circuit 112. Thedigital samples are supplied to the FFT circuit 104 which performs afast Fourier transform operation thereon. The digital samplescorresponding to each sub-carrier signal of the received OFDM signal aresupplied in parallel to the parallel to serial converter circuit 106.The circuit 106 converts the parallel input into a serial data streamwhich is supplied to the channel compensation circuit 108. The channelcompensation circuit 108 performs one or more signal processingoperations, e.g., filtering operations, designed to correct for signaldistortions introduced by the communications channel from which the OFDMsignal is received. The channel compensation circuit 108 uses channelinformation obtained from channel estimation circuit 110 when performingchannel compensation operations.

[0033] The OFDM receiver circuit 100 may, and in one embodiment is,followed by demodulator circuitry including circuits for performingdemapping, decoding and forward-error-correction functions.

[0034]FIG. 2 is a diagram 200 an exemplary ideal OFDM spectrum, whichcomprises a number of carriers. The vertical axis in FIG. 2 is afunction of signal energy while the horizontal axis is a function offrequency. OFDM carrier tones are spaced one horizontal integer unitapart in the FIG. 2 illustration. FIG. 3 is a diagram 300 which providesan expanded illustration of a portion of the OFDM spectrum shown in FIG.2. In FIG. 3 it can be seen that the energy of each OFDM carrier passesthrough zero at the surrounding carriers' center positions.

[0035]FIG. 4 is a diagram 400 showing an exemplary jitter spectrum. If alocal oscillator used for frequency conversion in the OFDM transmitteror receiver is contaminated by phase noise, it will no longer be aperfect sine wave, and therefore will have some finite spectral widthresulting in a spectrum such as that illustrated in FIG. 4. The phasenoise contaminated signal in FIG. 4 is in contrast to the impulsefunction that would occur if a perfect sine wave were plotted on theFIG. 4 chart. When the output of an oscillator having a signal such asthat shown in FIG. 4 is mixed, or multiplied, with the OFDM spectrum, ithas the effect of convolution in the frequency domain.

[0036]FIG. 5 is a diagram 500 showing the convolution of the exemplaryjitter spectrum shown in FIG. 4 with the exemplary ideal OFDM spectrumillustrated in FIG. 1. FIG. 6 is a diagram 600 which shows an expansionof a portion of the spectrum illustrated in FIG. 5. In FIG. 6 it can beclearly seen that the energy of each carrier now does not pass throughzero at the surrounding carriers' center positions as in the case of theideal OFDM spectrum shown in FIGS. 2 and 3. In FIG. 6, the carriers areno longer purely orthogonal, thereby resulting in inter-carrierinterference.

[0037]FIG. 7 illustrates an OFDM receiver circuit 700 implemented inaccordance with the invention. The circuit 700 includes a resamplingcircuit 102, FFT circuit 104, P/S circuit 106, channel compensationcircuit 108, channel estimation circuit 110, and a timing recoverycircuit 112 which are the same as, or similar to, the like namedcircuits described above in regard to FIG. 1. In addition to theseelements, the OFDM receiver circuit 700 includes a jitter compensationcircuit 702 implemented in accordance with the present invention. Thejitter compensation circuit 702 receives as its input, the output of thechannel compensation circuit 108, e.g., a block of samples upon whichchannel compensation has been performed. It also receives timinginformation from the timing recovery circuit 112.

[0038] The jitter compensation circuit 702 includes a buffer 704, ajitter compensation filter 706, and an error calculation circuit 708each of which receives timing information from timing recovery circuit112. In addition the compensation circuit 702 includes a filter updateand output control circuit 712 and a latch 710. The latch 710 has anenable input which is enabled by the filter update and output controlcircuit 712 when it determines that the filtering of the signal, e.g.,block of samples received from the channel compensation circuit 108during a symbol time period has undergone sufficient filtering. Theoutput of the latch 710 serves as the output of the jitter compensationcircuit 702 and is supplied, e.g., to subsequent demodulator circuitry.

[0039] The buffer 704 is used to receive and hold the output of thechannel estimation compensation circuit 108 so that it can be repeatedlyprocessed by the jitter compensation filter 706 prior to being output bythe OFDM receiver circuit 700.

[0040] The jitter compensation filter 706 is used to reduce and/orremove intercarrier interference caused by random jitter, e.g., prior todemodulation. The jitter compensation filter 706 is particularly wellsuited to reducing and/or eliminating jitter caused by, e.g., tunerphase noise. In order to allow the jitter compensation filter 702 toprocess a block of samples multiple times, the jitter compensationfilter operates at a clock rate which is a multiple of the sampling rateused to initially generate the digital signal being processed.

[0041] The error calculation circuit 708, is coupled to, and receives asits input, the filtered samples output by the jitter compensation filter706. The error calculation circuit 708 is used to calculate a filtercoefficient update signal, e.g., in the form of an error signal, used toadjust the jitter compensation filter's tap weights. After the filtertaps are updated by the error signal, the data stored in the buffer 704is filtered again. In this manner, the filter coefficients correspondingto the jitter compensation filter's taps are updated as part of aniterative process.

[0042] A fixed number of iterations, (e.g., filtering, error calculationand filter update cycles) may be set, or the iterations may be allowedto proceed until the system is deemed to have converged, e.g., at astable jitter compensation filter output result. The filter update andoutput control circuit 712 is responsible for determining, e.g., fromthe error signal and/or clock signals, when the selected filter outputcriteria have been satisfied.

[0043] Because phase jitter is generally uncorrelated from OFDM symbolto OFDM symbol, e.g., from FFT block to FFT block, in the exemplaryembodiment a new filter solution is generated for each input block. In acase where each symbol period is used to transmit a separate FFT block,the jitter compensation filter tap weights would be reset each symbolperiod. The jitter compensation filter 706 acts as an equalizer. Thefilter's taps may be set to an initial solution of, e.g., a unity centertap surrounded by zero taps, at the beginning of processing of eachblock of FFT values. This can be done by way of a reset signal, e.g., alatch enable and filter reset (LEFR) signal, generated by the filterupdate and output control circuit 712. The LEFR signal used to reset thefilter taps to their initial values is also used to enable the outputlatch 710.

[0044] The jitter compensation filter 706 can be trained for a fixednumber of iterations or the decision-directed error or other metric canbe examined to determine when the compensation filter taps haveadequately converged at which point the latch 710 is enabled and thejitter compensation tap weights reset for processing the next block ofsymbol values. The filter update and output control circuit 712 isresponsible for performing this function. The same signal, LEFR, whichstands for Latch Enable and Filter Reset, can be used to enable thelatch 710 and reset the tap weights in the jitter compensation filter706 to preselected, e.g., initial, values. In one embodiment, the outputcontrol circuit 712 enables the LEFR signal after a preselected numberof jitter compensation filter update cycles. In another embodiment, theLEFR signal is generated after the filter update and output controlcircuit determines from the error calculation circuit error output thatthe error estimate has ceased to improve but is improving by less than apreselected threshold amount with each iteration. After its assertionthe filter update and output control circuit de-asserts the LEFR signalso that filter updating starting from the initial values filter tapweight values may occur once again.

[0045] The jitter compensation filter 706 can, and in some embodimentsis, implemented as a finite impulse response (FIR) filter with adaptabletap weights, sometimes called filter coefficients. An exemplary jittercompensation filter 706 suitable for use in the system 700 is shown inFIG. 8.

[0046] In FIG. 8, the filter 706 is shown as having an adder 806 and aplurality of coefficient cells 802, 802′ 802″ arranged to form asequence of N filter cells, each cell corresponds to one filter tap. Thefirst filter cell, 802, in the sequence of N filter cells receives asits input the jitter compensation filter output. A cell output of thefirst filter cell 802 is coupled to the cell input of the next filtercell 802′, in the sequence of N filter cells. Thus, with the exceptionof the first filter cell 802, the Nth filter cell in the sequencereceives its cell input from the cell output of the preceding (N-1)filter cell. The output of the last filter cell (Nth) filter cell 802″in the sequence of N filter cells goes unused since there is nosubsequent filter cell.

[0047] Each of the filter cells also receives, as an input, errorinformation generated by the error calculation circuit 708. The errorinformation may be, e.g., tap weight update information, which is usedby the filter cells to update their internal tap weight or weights. Thetap weights may be reset to an initial value after processing the blockof data corresponding to a symbol period by way of the LEFR signal whichis used as a reset signal.

[0048] Each of the N filter cells 802, 802′, 802″ generates a cellproduct. The cell product from each filter cell is supplied as an inputto the adder 806. The adder 806 sums the cell products output by each ofthe N coefficient cells to generate the jitter compensation filter'soutput signal. Thus, the output of the jitter compensation filter 706 isthe summation of the outputs of the individual coefficient cells. Aswill be discussed below, the jitter compensation filter output signal isused by the error calculation circuit 708 to generate the errorinformation, used to update the jitter compensation filter's tap weightsto be used in the next iteration of the filtering process.

[0049] A first exemplary jitter compensation coefficient filter cell 802is shown in FIG. 9. The filter cell 802 comprises a register 902,conjugate circuit 904, a first multiplier 906, adaptive gain circuit908, adder 910, tap register 912 and a second multiplier 914. The tapregister 912 stores the filter coefficient, also sometimes called tapweight, used by the filter cell 802.

[0050] The shift register 902 is a delay element that serves as part ofthe general delay-line structure of the overall FIR jitter compensationfilter 706. The output of the register 902 is multiplied by thecoefficient value stored in tap register 912 thereby producing theoutput, e.g., cell product, of the coefficient cell 802.

[0051] The tap value is updated after each filtering operation as afunction of the received error signal (ERROR). In the FIG. 9 embodiment,the multiplier 906 multiplies the received error signal with theconjugate of the value output by the shift register 902. The multiplieroutput value is then scaled by gain circuit 908 by an amount set withinthe circuit 908. The scaled multiplier output is supplied to asubtracting input of adder 910 which further receives, at an addinginput, the current value stored in tap register 912. The resultingcorrected filter coefficient value, generated by subtracting the scaledmultiplier output value from the current filter coefficient value, isstored in tap register 912 in time to be used during the next filteringoperation.

[0052] In the above described manner, the value of tap stored inregister 912, is updated by subtracting, through an adder 910 acorrection signal which is the product, scaled by an adaptation gain, ofthe error signal received from the error calculation block and theconjugate of the data stored in shift register 902. This approachrepresents a least-mean-square (LMS) update technique. Other tap weightupdating mechanisms may be employed instead of, or in addition to, thedescribed LMS update technique.

[0053] A first exemplary error calculation circuit 804 is shown in FIG.10. The error calculation circuit 804 comprises a slicer 1002, first andsecond summers 1004, 1018, a squaring circuit 1006, accumulator 1008,register 1010 comparator 1012, first multiplexer 1014, secondmultiplexer 1016 and a pilot information circuit 1020 which are coupledtogether as illustrated in FIG. 10.

[0054] During operation, an incoming signal, e.g., a block of samplesrepresenting symbols output by the jitter compensation filter, issubject to slicing by the slicer 1002. The difference, produced bysummer 104 which subtracts the slicer output from an input symbol,produces a decision-directed error. The decision-directed errors, e.g.,one per received symbol, output by summer 1004 are squared and thensummed by accumulator 1008. The accumulator 1008 produces an averageerror metric referred to as “MSE” for mean-squared error. At the end ofprocessing the symbols included within the current OFDM block beingfiltered, the register REG 1010 is clocked to store the resulting MSEvalue, and the accumulator 1008 is reset to zero to prepare foraccumulating in the next iteration. Local reset control 1005 isresponsible for generating the accumulator reset signal, e.g., fromreceived timing information.

[0055] The first comparator 1012 is used to compare the output value REGof register 1010 to a threshold MSE_THRESHOLD, e.g., a value set at orprior to system implementation. When it is determined that the value REGis below the threshold MSE_THRESHOLD, the signal being filtered isdeemed to have converged sufficiently that decision-directed errors maybe used beneficially in updating the compensation filter tap weights andthe output of the first comparator 1012 is asserted.

[0056] The select input of the first multiplexer MUX1 1014 causes themultiplexer to output the decision-directed error supplied to its firstinput when REG is asserted (1), e.g., the signal being processed hasconverged sufficiently for the decision directed error to be usedreliably. When the value of REG exceeds the MSE_THRESHOLD, indicating ahigh error rate, the signal being processed is deemed not to haveconverged sufficiently to the point where decision-directed errors canbe used reliably in updating the compensation filter tap weights and theoutput of the first comparator 1012 will not be asserted (0) causing thefirst multiplexer 1014 to output the zero supplied to the firstmultiplexer's second input. In the illustrated embodiment, themultiplexer MUX1 1014 multiplexes a zero error for use on signals withnon-pilot carriers in the case where the signal being processed has notsufficiently converged for the decision directed error to be used toupdate the jitter filter tap values.

[0057] Pilot carriers are known carrier values that are oftentransmitted within an OFDM signal. Since they are known values, areliable pilot-directed error signal can be formed during the pilottimes, e.g., the times at which a pilot symbol is being processed. Thepilot values are stored somewhere within the receiver and can be usedfor error determination purposes when a pilot symbol is being processed.In the FIG. 10 example, a PILOT INFO block 1020, which receives timinginformation, is shown as storing the pilot value information. However,since pilot information is used in the channel estimation process, thatinformation may alternatively be stored in the channel estimation block110 and supplied to the error calculation circuit as needed.

[0058] The error calculation circuit 804 calculates a pilot directederror by using the second adder 1018 to subtract the pilot symbol valuefrom the received symbol value. The resulting pilot directed error issupplied to the second input of the second multiplexer 1016 while thedecision director error (or zero error value) output by the first MUX11014 is supplied to the second multiplexer's first input.

[0059] In accordance with the exemplary embodiment of the presentinvention illustrated in FIG. 10, when possible, pilot directed errorsare used instead of decision directed errors to generate the errorsignal used to update the jitter compensation filter tap values. Thesecond multiplexer MUX2 1016 is used to control when a pilot directederror as opposed to a decision directed error will be used to update thejitter compensation filter 706.

[0060] The second multiplexer MUX2 1016 is used to control whether thedecision directed error output by MUX1 1014 or the pilot directed errorgenerated by summer 1018 is used as the error output signal. The selectsignal used to determine the output of MUX2 1016 is a pilot valid signalreceived as part of the timing information. The pilot valid signalindicates a pilot symbol is being processed and thus, when the pilotdirected error will be valid and should be used.

[0061] When pilot symbols are being processed, the select signalsupplied to multiplexer MUX2 1016 will be asserted (1) causing the pilotdirector error signal to be used as the error calculation circuit'serror output signal. However, during other times the select signal willbe de-asserted (0) resulting in the output of the first MUX1 1014 beingused as the error output signal of the error calculation circuit 804.

[0062] As an alternative to declaring zero error when the signal beingfiltered is noisy and pilot symbols are not being processed, an errorsignal for the non-pilot tones can be calculated via anon-decision-directed method. Then when the MSE falls below somepredefined threshold, e.g., the MSE_THRESHOLD, the decision directederror generated by the non-pilot tones can be used in updating thejitter compensation filter 706.

[0063]FIG. 11 illustrates a second exemplary error calculation circuit804′ which is similar to the circuit 804 shown in FIG. 10. The FIG. 11circuit differs from the FIG. 10 circuit in that it uses a non-decisiondirected error calculation method when the decision directed error andthe pilot directed error values are not used.

[0064] One non-decision-directed error calculation method is theconstant-modulus algorithm, which calculates the error as

ERR=Z*(|Z| ² −R ₀ ²),

[0065] where the modulus R₀ ² is defined as

R ₀ ² =<|Z _(SL) | ⁴ >/<|Z _(SL)|²>,

[0066] where the averaging denoted by <> is over all of the ideal(“sliced”) constellation points Z_(SL).

[0067] In the FIG. 11 embodiment, the error calculation circuit 804′includes a constant modulus error generation circuit 1102 whichgenerates a constant modulus error value from the received input but isotherwise similar to the circuit 804. The output of the constant moduluserror circuit 1102 is supplied to the second input of the first MUX11014 as opposed to a zero which was supplied in the FIG. 10 embodiment.As a result, the constant modulus error signal will be used as the errorcalculation circuit's output signal when the decision directed error andthe pilot directed errors are not used.

[0068] In accordance with the present invention, jitter compensationcircuit operates at a rate which is faster, e.g., at a clock rateseveral times the clock rate of the channel compensation circuit andvarious other OFDM receiver circuits. This allows the same signal, e.g.,set or block of values, output by the channel compensation circuit to beprocessed several times by the jitter compensation circuit 702 beforebeing output, e.g., to subsequent demodulator circuitry.

[0069] An alternative to operating the jitter compensation circuit at aclock rate several times the clock rate of the various other OFDMreceiver circuits is to utilize parallel hardware: for example, multiplejitter compensation filters and error calculation circuits, such thatthe output of one circuit feeds into the subsequent circuit. This wouldintroduce overall latency into the system, but reduce the processingspeed, i.e., clock rate required.

[0070] In order to support reprocessing of the input signal multipletimes the jitter compensation circuit includes a buffer 704 for storingthe input signal. However, for this purpose, the signal may be storedwithin the parallel-to-serial converter (106), or possibly an alternatestorage location following the channel compensation block.

[0071] In accordance with the present invention, each time the signal isrun through the jitter compensation filter 706, the compensation filtertaps are trained and the output normally becomes more reliable as thefilter taps converge to a good solution.

[0072] Jitter compensation filter refinement in the above describemanner can, in many cases, make a previously unusable signal usable.Thus, it allows the use of more inexpensive analog components (tuners)having a high amount of phase noise then would otherwise be acceptable.

[0073]FIG. 12 shows the initial value of taps in an exemplary 51-tapjitter compensation filter. In the FIG. 12 example the 51-tap filter hasa center tap initialized to one, and the other taps initialized to zero.

[0074]FIG. 13 shows a constellation of 1024 symbols represented by theblock of bits, i.e., the signal being processed by the jittercompensation circuitry, after a first pass, that is, without any jittercompensation.

[0075]FIG. 14 shows a set of filter taps (in absolute value) resultingafter six iterations of filter updating in accordance with the presentinvention.

[0076]FIG. 15 shows the output of the jitter compensation filter 706 onthe same exemplary signal which resulted in the FIG. 13 plot, after thesixth iteration of updating the jitter compensation filter. Note thatthe 16-QAM constellation points carried over the each of the OFDMcarriers are now clearly distinguishable, and hence the previouslyunrecoverable data is now recoverable as a result of the jittercompensation filtering of the present invention.

[0077] The methods and apparatus of the present invention have beendescribed in the context of an OFDM receiver application which may beused, e.g., for wireless local area networks, multi-channel multipointdistribution systems (MMDS), or terrestrial broadcast purposes, in orderto allow inexpensive tuners, having otherwise excessive phase noise, tobe used. While described in an OFDM embodiment, the methods andapparatus of the present invention are not limited to OFDM applicationsand can be used in other types of receivers which process multi-tonesignals. Furthermore, while described in terms of circuits, the elementswhich make up the apparatus of the present invention can be implementedas software modules which can be used to control a programmableprocessor to perform the described signal processing operations.Accordingly, the present invention encompasses software as well ascircuitry for implementing the above described methods.

What is claimed is:
 1. An apparatus for processing a block of datarepresenting at least one symbol, the apparatus comprising: a jittercompensation filter for performing a filtering operation on said blockof data to generate a filtered block of data, the jitter compensationfilter having an update input for receiving a filter coefficient updatesignal; and an error calculation module coupled to the update input ofthe jitter compensation filter, the error compensation module generatingthe filter coefficient update signal from at least one signal errorestimate made from the filtered block of data output by the jittercompensation filter.
 2. The apparatus of claim 1, further comprising: acontrol circuit coupled to said error calculation circuit fordetermining as a function of said at least one error estimate, when tooutput said filtered block of data.
 3. The apparatus of claim 1, furthercomprising: a channel compensation circuit for receiving said block ofdata and performing a channel compensation operation on at least aportion of said block of data prior to the block of data being processedby said jitter compensation filter.
 4. The apparatus of claim 3, whereinsaid block of data represents a plurality of symbols, the apparatusfurther comprising: demodulator circuitry coupled to an output of thejitter compensation filter.
 5. The apparatus of claim 1, where the errorcalculation module includes: means for generating a decision directederror value.
 6. The apparatus of claim 5, wherein the error calculationmodule further includes: means for generating a pilot directed errorvalue; and a selection device for selecting one of the decision directederror value and the pilot directed error value to be output.
 7. Theapparatus of claim 5, wherein said error estimation module futureincludes: means for generating a non-decision directed error value; anda selection device for selecting one of the decision directed errorvalue and the non-decision directed error value to be output.
 9. Theapparatus of claim 1, where the error calculation module includes: meansfor generating a non-decision directed error value.
 10. The apparatus ofclaim 1, further comprising: an input buffer for storing said block ofdata while it is processed multiple times by said jitter compensationfilter.
 11. The apparatus of claim 10, further comprising: an outputcontrol device for determining when to output the filtered block of datagenerated by said jitter compensation filter.
 12. The apparatus of claim11, wherein the output control device includes: means for determiningwhen said block of data has been filtered a fixed number of times by thejitter compensation filter.
 13. The apparatus of claim 11, wherein theoutput control device includes an input for receiving the filtercoefficient update signal generated by said error calculation module;and wherein the jitter compensation filter further includes means forresetting filter coefficient values to a set of initial values inresponse to a reset signal generated by said output control device. 14.A system for processing a multi-tone signal, the system including: achannel compensation module for performing a channel compensationoperation on said multi-tone signal; and a jitter compensation modulecoupled to an output of the channel compensation module for performing ajitter reduction operation on the channel compensated multi-tone signal.15. The system of claim 14, wherein the jitter compensation moduleincludes: a jitter compensation filter with programmable filter tapweights; and means for iteratively updating the filter tap weights as afunction of the jitter compensation filter output.
 16. The system ofclaim 15, further comprising; a control circuit for determining when theoutput of the jitter compensation filter should be used as the output ofthe jitter compensation module.
 17. The system of claim 15, wherein themeans for iteratively updating the filter tap weights includes: a signalerror estimation circuit for generating from the output of the jittercompensation filter a measure of a symbol error.
 18. The system of claim17, further comprising: means for resetting the jitter compensationfilter tap weights to an initial set of values in response to thecontrol circuit determining that the output of the jitter compensationfilter should be used as the output of the jitter compensation filter.19. A method of using a filter having a plurality of tap weights toreduce the effect of phase jitter on a block of data representing atleast one transmitted symbol, the method comprising the steps of: i)operating said filter to filter said block of samples to produce afiltered block of data; ii) determining a signal error from the filteredblock of data; iii) updating at least one of said plurality of tapweights in said filter as a function of the determined signal error; andiv) repeating steps i, ii, and iii until a filter updating stopcriterion is satisfied.
 20. The method of claim 19, further comprisingthe step of: supplying the filtered block of data output by said filterwhen said filter updating criterion is satisfied to subsequent receivercircuitry.
 21. The method of claim 19, wherein said filter updating stopcriterion is the completion of a fixed number of filtering operations onsaid block of data.
 22. The method of claim 21, wherein said filterupdating criterion is a failure in the signal error to exhibit animprovement over the previous signal error.
 23. The method of claim 19,wherein said step of determining a signal error includes generating adecision directed error value.
 24. The method of claim 19, wherein saidstep of determining a signal error includes generating a non-decisiondirected error value.
 25. The method of claim 19, further comprising:prior to performing step i, performing a channel compensation operationon said block of data.
 26. The method of claim 25, a single channelcompensation operation is performed on the block of data in a firstperiod of time; and step i, ii and iii are performed multiple times in atime period which is equal to or shorter than the first time period.